rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a octal sample-and-hold with multiplexed input SMP08* functional block diagram sw sw sw sw sw sw sw sw 1 of 8 decoder 6 9 10 11 3 13 16 8 14 15 12 7 1 2 4 5 dgnd v dd ch 0 out ch 1 out ch 2 out ch 3 out ch 4 out ch 5 out ch 6 out ch 7 out v ss hold caps (internal) SMP08 input (lsb) a b (msb) c inh features internal hold capacitors low droop rate ttl/cmos compatible logic inputs single or dual supply operation break-before-make channel addressing compatible with cd4051 pinout low cost applications multiple path timing deskew for ate memory programmers mass flow/process control systems multichannel data acquisition systems robotics and control systems medical and analytical instrumentation event analysis stage lighting control general description the SMP08 is a monolithic octal sample-and-hold; it has eight internal buffer amplifiers, input multiplexer, and internal hold capacitors. it is manufactured in an advanced oxide isolated cmos technology to obtain high accuracy, low droop rate, and fast acquisition time. the SMP08 has a typical linearity error of only 0.01% and can accurately acquire a 10-bit input signal to 1/2 lsb in less than 7 microseconds. the SMP08s output swing includes the negative supply in both single and dual sup- ply operation. the SMP08 was specifically designed for systems that use a calibration cycle to adjust a multiple of system parameters. the low cost and high level of integration make the SMP08 ideal for calibration requirements that have previously required an asic, or high cost multiple d/a converters. * protected by u.s. patent no. 4,739,281. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1996 the SMP08 is also ideally suited for a wide variety of sample- and-hold applications including amplifier offset or vca gain adjustments. one or more SMP08s can be used with single or multiple dacs to provide multiple set points within a system. the SMP08 offers significant cost and size reduction over dis- crete designs. it is available in a 16-pin plastic dip, or surface- mount soic package.
C2C SMP08Cspecifications electrical characteristics parameter symbol conditions min typ max units linearity error C3 v v in +3 v 0.01 % buffer offset voltage v os t a = +25 c, v in = 0 v 2.5 10 mv C40 c t a +85 c, v in = 0 v 3.5 20 mv hold step v hs v in = 0 v, t a = +25 c to +85 c 2.5 4 mv v in = 0 v, t a = C40 c5mv droop rate d v ch / d tt a = +25 c, v in = 0 v 2 20 mv/s output source current i source v in = 0 v 1 1.2 ma output sink current i sink v in = 0 v 1 0.5 ma output voltage range r l = 20 k w C3.0 +3.0 v logic characteristics logic input high voltage v inh 2.4 v logic input low voltage v inl 0.8 v logic input current i in v in = 2.4 v 0.5 1 m a dynamic performance 2 acquisition time 3 t aq t a = +25 c, C3 v to +3 v to 0.1% 3.6 7 m s hold mode settling time t h to 1 mv of final value 1 m s channel select time t ch 90 ns channel deselect time t dcs 45 ns inhibit recovery time t ir 90 ns slew rate sr 3 v/ m s capacitive load stability <30% overshoot 500 pf analog crosstalk C3 v to +3 v step C72 db supply characteristics power supply rejection ratio psrr v s = 5 v to 6 v 60 75 db supply current i dd t a = +25 c 4 7.5 ma C40 c t a +85 c 5 9.5 ma electrical characteristics parameter symbol conditions min typ max units linearity error 60 mv v in 10 v 0.01 % buffer offset voltage v os t a = +25 c, v in = 6 v 2.5 10 mv C40 c t a +85 c, v in = 6 v 3.5 20 mv hold step v hs v in = 6 v, t a = +25 c to +85 c 2.5 4 mv v in = 6 v, t a = C40 c5mv droop rate d v ch / d tt a = +25 c, v in = 6 v 2 20 mv/s output source current i source v in = 6 v 1 1.2 ma output sink current i sink v in = 6 v 1 0.5 ma output voltage range r l = 20 k w 0.06 10.0 v r l = 10 k w 0.06 9.5 v logic characteristics logic input high voltage v inh 2.4 v logic input low voltage v inl 0.8 v logic input current i in v in = 2.4 v 0.5 1 m a dynamic performance 2 acquisition time 3 t aq t a = +25 c, 0 v to 10 v to 0.1% 3.5 4.25 m s C40 c t a +85 c 3.75 6.00 m s hold mode settling time t h to 1 mv of final value 1 m s channel select time t ch 90 ns channel deselect time t dcs 45 ns inhibit recovery time t ir 90 ns slew rate sr r l = 20 k w 4 34 v/ m s capacitive load stability <30% overshoot 500 pf analog crosstalk 0 v to 10 v step C72 db supply characteristics power supply rejection ratio psrr 10.8 v v dd 13.2 v 60 75 db supply current i dd t a = +25 c 6.0 8.0 ma C40 c t a +85 c 8.0 10.0 ma notes 1 outputs are capable of sinking and sourcing over 20 ma but offset is guaranteed at specified load levels. 2 all input control signals are specified with t r = t f = 5 ns (10% to 90% of +5 v) and timed from a voltage level of 1.6 v. 3 this parameter is guaranteed without test. 4 slew rate is measured in the sample mode with 0 v to 10 v step from 20% to 80%. specifications subject to change without notice. (@ v dd = +5 v, v ss = C5 v, dgnd = 0 v, r l = no load, t a = C40 8 c to +85 8 c for SMP08f, unless otherwise noted) (@ v dd = +12 v, v ss = 0 v, dgnd = 0 v, r l = no load, t a = C40 8 c to +85 8 c for SMP08f, unless otherwise noted) rev. d
SMP08 C3C rev. d absolute maximum ratings v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, 17 v v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, 17 v v logic to dgnd . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, v dd v in to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ss , v dd v out to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ss , v dd analog output current . . . . . . . . . . . . . . . . . . . . . . . 20 ma (not short-circuit protected) operating temperature range fp, fs . . . . . . . . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . +150 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 60 sec) . . . . . . . . . . . . +300 c package type u ja * u jc units 16-pin plastic dip (p) 76 33 c/w 16-pin soic (s) 92 27 c/w * q ja is specified for worst case mounting conditions, i.e., q ja is specified for device in socket for plastic dip package; q ja is specified for device soldered to printed circuit board for so package. ordering guide temperature package package model range description option SMP08fp C40 c to +85 c plastic dip n-16 SMP08fs C40 c to +85 c so-16 r-16a pin connections 14 13 12 11 16 15 10 9 8 1 2 3 4 7 6 5 top view (not to scale) SMP08 ch 4 out ch 0 out ch 1 out ch 2 out v dd ch 6 out input ch 7 out b control a control ch 3 out ch 5 out inh v ss dgnd c control warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the SMP08 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
C4C input voltage ?volts droop rate ?mv/s 1800 1200 600 01 10 23456789 1600 1400 1000 800 v dd = +12v v ss = 0v t a = +125 c no load figure 3. droop rate vs. input voltage v dd ?volts slew rate ?v/? 7 6 3 10 11 18 12 13 14 15 16 17 5 4 v ss = 0v t a = +25 c no load ?r +sr figure 6. slew rate vs. v dd input voltage ?volts offset voltage ?mv 4 ?0 01 10 23456789 2 0 ? ? ? ? v dd = +12v v ss = 0v t a = ?0 c no load r l = r l = 20k w r l = 10k w figure 9. offset voltage vs. input voltage input voltage ?volts droop rate ?mv/s 3 0 ? 01 10 23 4 5 67 8 9 2 1 ? ? v dd = +12v v ss = 0v t a = +25 c no load figure 2. d roop rate vs. input voltage temperature ? c hold step ?mv 2 ? ?5 ?5 85 155 254565 1 0 ? ? ? v dd = +12v v ss = 0v v in = +5v no load figure 5. hold step vs. temperature input voltage ?volts offset voltage ?mv 20 5 ?0 01 10 23456789 15 10 ? ?5 0 ?0 v dd = +12v v ss = 0v t a = +85 c no load r l = r l = 20k w r l = 10k w figure 8. offset voltage vs. input voltage rev. d SMP08Ctypical performance characteristics temperature ? c droop rate ?mv/s 1000 100 0.1 ?5 ?5 125 ?5 5 25 65 85 105 45 10 1 v dd = +12v v ss = 0v v in = +5v r l = 10k w figure 1. droop rate vs. temperature input voltage ?volts hold step ?mv 2 ? ? 01 10 23456789 1 0 ? ? v dd = +12v v ss = 0v t a = +25 c no load figure 4. hold step vs. input voltage input voltage ?volts offset voltage ?mv 4 ?0 01 10 23456789 2 0 ? ? ? ? v dd = +12v v ss = 0v t a = +25 c no load r l = r l = 20k w r l = 10k w figure 7. offset voltage vs. input voltage
temperature ? c offset voltage ?mv 0 ? ?5 ?5 125 ?5 5 25 65 85 105 45 ? ? ? ? ? ? ? v dd = +12v v ss = 0v v in = +5v r l = 10k w figure 10. offset voltage vs. temperature v dd ?volts supply current ?ma 14 2 46 18 8 10121416 12 10 8 6 4 v ss = 0v no load +85 c +25 c ?0 c figure 11. supply current vs. v dd frequency ?hz 90 80 0 10 100 1m 1k 10k 100k 70 60 20 50 40 30 10 rejection ratio ?db v dd = +12v v ss = 0v v in = +6v t a = +25 c no load +psrr ?srr figure 12. sample mode power supply rejection typical performance characteristicsCSMP08 rev. d C5C frequency ?hz gain ?db 2 1 ? 100 1k 10m 10k 100k 1m 0 ? ? ? ? 90 45 ?25 0 ?5 ?0 ?35 ?80 phase shift ?degrees v dd = +12v v ss = 0v t a = +25 c no load gain phase figure 13. gain, phase shift vs. frequency frequency ?hz peak-to-peak output ?volts 15 12 0 10k 100k 10m 1m 9 6 3 v dd = +6v v ss = ?v t a = +25 c no load figure 15. maximum output voltage vs. frequency frequency ?hz output impedance ? w 35 30 0 10 100 1m 1k 10k 100k 25 20 15 10 5 v dd = +12v v ss = 0v t a = +25 c no load figure 14. output impedance vs. frequency frequency ?hz rejection ratio ?db 60 50 ?0 10 100 1m 1k 10k 100k 40 30 20 10 0 v dd = +12v v ss = 0v t a = +25 c no load +psrr hold capacitors referenced to v ss ?srr figure 16. hold mode power supply rejection
SMP08 C6C rev. d 14 13 12 11 16 15 10 9 8 1 2 3 4 7 6 5 SMP08 r2 10k w r2 10k w r2 10k w r2 10k w r3 6.5k w r4 1k w r1 10 w d1 c1 10? c2 1? + v cc +15v r2 10k w r2 10k w r2 10k w r2 10k w figure 17. burn-in circuit output buffers (pins 1, 2, 4, 5, 12, 13, 14, 15) the bu ffer offset specification is 10 mv; this is less than 1/2 lsb of an 8-bit dac with 10 v full scale. the hold step (magni- tude of s tep caused in the output voltage when switching from sample- to-hold mode, also referred to as the pedestal error or sample-to-hold offset), is about 2.5 mv with little variation over the full output voltage range, t a = +25 c to +85 c. the droop rate of a held channel is 2 m v/s typical and 20 mv/s maximum. the buffers are designed to drive loads connected to ground. the outputs can source more than 20 ma, over the full voltage range, but have limited current sinking capability near v ss . in split supply operation, symmetrical output swings can be ob- tained by restricting the o utput range to 2 v from either supply. on-chip SMP08 buffers eliminate potential stability problems associated with external buffers; outputs are stable with ca- pacitive loads up to 500 pf. however, since the SMP08s buffer outputs are not short-circuit protected, care should be taken to avoid shorting any output to the supplies or ground. signal input (pin 3) the signal input should be driven from a low impedance volt- age source such as the output of an op amp. the op amp should have a high slew rate and fast settling time if the SMP08s acquisition time characteristics are to be maintained. as with all cmos devices, all input voltages should be kept within range of the supply rails (v ss < v in < v dd ) to avoid the possibility of latchup. if single supply operation is desired, op amps such as the op183 or ad820 that have input and output voltage compliances including ground, can be used to drive the inputs. split supplies, such as 7.5 v, can be used with the SMP08. application tips all unused digital inputs should be connected to logic low and unused analog inputs connected to analog ground. for connector-driven analog inputs that may become temporarily disconnected, a resistor to v dd , v ss or analog ground should be used with a value ranging from 200 k w to 1 m w . applications information the SMP08, a multiplexed octal s/h, minimizes board space in systems requiring cycled calibration or an array of control volt- ages. when used in conjunction with a low cost 16-bit d/a, the SMP08 can easily be integrated into microprocessor based sys- tems. since the SMP08 features break-before-make switching and an internal decoder, no external logic is required. the SMP08 has an internally regulated ttl supply so that ttl/ cmos compatibility is maintained over the full supply range. see figure 18 for channel decode address information. power supplies the SMP08 is capable of operating with either single or dual supplies, over a voltage range of 7 volts to 15 volts. based on the supply voltages chosen, v dd and v ss establish the input and output voltage range, which is: ( v ss +0.06 v ) v out/in ( v dd C2 v ) note that several specifications, including acquisition time, off- set and output voltage compliance, will degrade for supply volt- ages of less than 7 v. if split supplies are used, the negative supply should be bypassed with a 0.1 m f capacitor in parallel with a 10 m f to ground. the internal hold capacitors are connected to this supply pin and any noise will appear at the outputs. in single supply applications, it is extremely important that the v ss (negative supply) pin is connected to a clean ground. the hold capacitors are internally tied to the v ss (negative) rail. any ground noise or disturbance will directly couple to the output of the sample-and-hold, degrading the signal-to-noise perfor- mance. the analog and digital ground traces on the circuit board should be physically separated to reduce digital switching noise from entering the analog circuitry. power supply sequencing v dd should be applied to the SMP08 before the logic input sig- nals. the SMP08 has been designed to be immune to latchup, but standard precautions should still be taken.
SMP08 C7C rev. d v ss v ss v ss v ss v ss v ss v ss v ss SMP08 13 14 15 12 1 2 4 5 3 16 6 7 8 9 10 11 +12v ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 3 15 1 5 16 17 4 +12v +5v ref02 +12v v ref av dd v oa v z gnd wr cs dac8228 a b c address decode address bus digital inputs wr dgnd inh 0.1? pin 9 c pin 10 b pin 11 a pin 6 inh ch pin 0 0 0 0 1 1 1 1 x 0 0 1 1 0 0 1 1 x 0 1 0 1 0 1 0 1 x 0 0 0 0 0 0 0 0 1 0 1 2 3 4 5 6 7 none 13 14 15 12 1 5 2 4 channel decoding figure 18. 8-channel multiplexed d/a converter do not apply signals to the SMP08 with power off unless the input current is limited to less than 10 ma. typical applications an 8-channel multiplexed d/a converter figure 18 illustrates a typical demultiplexing function of the SMP08. it is used to sample-and-hold eight different output voltages corresponding to eight different digital codes from a d/a converter. the SMP08s droop rate of 20 mv/s requires a refresh once every 500 ms, before the voltage drifts beyond 1/2 lsb accuracy (1 lsb of an 8-bit dac is equivalent to 19.5 mv out of a full-scale voltage of 5 v). for a 10-bit dac the refresh rate must be less than 120 ms, and, for a 12-bit system, 31 ms. this implementation is very cost effective com- pared to using multiple dacs as the number of output channels increases.
SMP08 C8C rev. d c2192C2C10/96 printed in u.s.a. outline dimensions dimensions shown in inches and (mm). 16-lead plastic dip (n-16) 16 18 9 0.840 (21.33) 0.745 (18.93) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 16-lead soic (narrow body) (so-16) 16 9 8 1 0.3937 (10.00) 0.3859 (9.80) 0.2550 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (5.80) pin 1 seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) bsc 0.0099 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45
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